Intro

What’s VHDL

synthesizers and stuff

VHDL describes hardware

VHDL describes hardware, not programs – Many electronics teachers

I agree with the first part of the sentence, but not really with the second.

If it describes a behavior, sounds like a program to me. It’s a declarative program, but it is a program.

Also, there are simulators that compile the program to a runnable binary so it’s faster to simulate. Maybe you are not writing C, but you can make a program with it! And even run it! It’s not designed for that and it lacks all the interesting things a general purpose programming language would have, like system calls and stuff like that, but you can write programs and run them.

The mindset has to be that, though. We have to think we are describing things. Many of the things in VHDL (and other HDLs) happen in parallel, but the syntax looks like an imperative programming language sometimes. Don’t let the syntax trick you.

The best you can do is stay focused in the circuit you are representing.

Why make a language for this?

It’s easier to manage, escalate and all that kind of things. We can use git!

Software to get started

• GHDL -> not available in my distro
• NVC -> available (not a synthesizer)

Notes about the syntax

• It’s case insensitive
• Line comments are written with --

VHDL concepts

• Entity: describes how the component looks from the outside
• Architecture: describes how the component works in the inside

One entity may have many architectures.

First example

entity and_gate is
    port (
        A : in bit;
        B : in bit;
        O : out bit
    );
end and_gate;

Better than bit is to use std_logic. Bit only can be 1 or 0 but std_logic can have other values like low voltage 1s, mixed values and so on. It’s way better for simulation. It requires the following import:

library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

Now we only have how the element looks from the outside, we have to implement the architecture.

architecture and_gate_internals of and_gate is
-- you can declare internal signals and constants here with `signal name : type;`
begin
    O <= A and B; -- NOTE: These are concurrent, so the order doesn't matter
end and_gate_internals;